Controlled reactance regulator circuit

ABSTRACT

A circuit for providing a regulated a-c or d-c output voltage from an unregulated a-c input voltage. A series inductance is connected between the regulator input and the regulator output to support the difference in voltage between the unregulated a-c input voltage and the regulated a-c or d-c output voltage. A controllable shunt reactance is connected to the source of input voltage, through the series inductance, to vary the current through and the voltage across the series inductance. Control circuitry controls the magnitude of the current which the shunt reactance draws through the line inductance, as required, to establish and maintain the regulated output voltage at the desired output current.

BACKGROUND OF THE INVENTION

The present invention relates to voltage regulating circuits and isdirected more particularly to voltage regulating circuits wherein acontrollable shunt reactance varies the voltage induced across aninductor, as required, to maintain that induced voltage equal to thedifference in voltage between an unregulated input voltage and aregulated output voltage.

Voltage regulators utilizing series-connected inductors in associationwith shunt-connected capacitors have long been known and used forproviding a substantially constant output voltage from an unregulateda-c input voltage. Early forms of such regulators were known asferroresonant regulators and utilized series-connected inductorstogether with shunt-connected networks which included capacitors andsaturable core magnetic units. Such concepts are shown, for example, inU.S. Pat. No. 2,143,745 granted to J. G. Sola on Jan. 10, 1939, and U.S.Pat. No. 2,377,152 granted in the name of H. M. Huge on May 29, 1945.Because of the excessive weight and audible noise associated with thesesaturable core magnetic units and because of the difficulty of obtainingan output voltage waveform of satisfactory harmonic content, manyattempts have been made to improve upon ferroresonant type voltageregulators.

One attempt to improve upon ferroresonant voltage regulators hasinvolved the substitution of a plurality of series-connected, saturablecore magnetic units for each single saturable core magnetic unitthereof. such substitutions are shown, for example, in U.S. Pat. No.3,092,768 granted in the name of A. Kusko on June 4, 1963 and U.S. Pat.No. 3,139,577 granted in the name of D. Krezek on June 30, 1964. Incircuits of the latter type, the seies-connected magnetic units saturatein a predetermined sequence to generate a waveform which isapproximately sinusoidal. While circuitry of this type can provide awaveform of satisfactory harmonic content, it increases the complexityand cost of the regulator without eliminating the problems of excessiveweight and audible noise.

Another attempt to improve ferroresonant voltage regulators has involvedthe substitution of gate controlled switching devices and linearinductances for each saturable core magnetic unit. Such substitutionsare shown, for example, in U.S. Pat. No. 3,076,924 granted in the nameof E. W. Manteuffel on Feb. 5, 1963. In such circuits, the linearinductance simulated the saturated impedance of a saturable coremagnetic unit and the gate controlled switching devices simulated off-onconducting characteristic thereof. While the utilization of suchsolid-state circuitry did reduce the weight and noise associated withferroresonant voltage regulators, it did not solve the problem ofreducing the high harmonic content of its output voltage. In addition,such solid-state circuitry did not lend itself to use in true threephase voltage regulators. As a result, polyphase forms of suchsolid-state regulator circuits were produced by the uneconomicalexpedient of coupling together a plurality of single-phase solid-stateregulator circuits.

A still more recent attempt to solve the above-described problem isdescribed in U.S. Pat. No. 3,745,437 granted in my name on July 10,1973. The circuitry shown and described in that patent will hereinafterbe referred to as the circuitry of my earlier patent. While thecircuitry of my earlier patent solves the problem of providing a truepolyphase regulator circuit having an output voltage of acceptableharmonic content, it does not satisfactorily deal with certain practicalproblems which prevent that circuitry from being economical. In thecircuitry of my earlier patent, it is, for example, desirable to utilizerelatively expensive circuit components having special operatingcharacteristics. Thyristors which can turn on and off in very shorttimes are typically necessary. High performance core materials and lowinductance capacitors are also typically necessary. Thus, while thecircuitry of my earlier patent is a useful and operative structure, ithas certain practical deficiencies. An additional disadvantage of thecircuitry described in my earlier patent is that it produces substantialamounts of audible noise. This audible noise, in turn, imposes furtherpractical limitations on the usefulness of the circuitry since themagnetic units must ordinarily be potted and the circuit as a wholesurrounded by sound absorbing materials.

In accordance with the present invention, there is provided polyphaseregulating circuitry which exhibits all of the numerous advantages ofthe regulating scheme described in my earlier patent, which isrealizable with magnetic units utilizing ordinary core materials andordinary winding configurations, and which utilizes ordinary capacitorsand ordinary semiconductor devices. In addition, the regulating circuitof the present invention eliminates the problem of excessive audiblenoise and produces an output waveform of harmonic content which is evenlower than that produced by the circuit of my earlier patent. Thus, thecircuit of the present invention is a significant improvement over thevoltage regulator circuit of my earlier patent.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an improved voltageregulator circuit of the type wherein the output voltage is determinedby the effect of a controllable shunt reactance on an inductor connectedbetween the regulator input and the regulator output.

An additional object of the invention is to provide an improved voltageregulator circuit of the above type in which the waveform of the voltageacross the shunt reactance is determined by a programmed redistributionof charge among a plurality of capacitors.

Another object of the invention is to provide an improved voltageregulator circuit which need not utilize magnetic devices, capacitors orsemiconductor devices having special operating characteristics.

Still another object of the invention is to provide a voltage regulatorcircuit of the above type wherein the voltage across the controllableshunt reactance has an improved waveform of lower harmonic content.

Another object of the invention is to provide a regulator circuit of theabove type in which each redistribution of charge among the capacitorsis accomplished as a result of the timed initiation of a resonantcurrent pulse, each resonant current pulse having a frequency of fromthree to ten times the frequency of the unregulated a-c input voltage.

Yet another object of the invention is to provide an improved polyphasevoltage regulator circuit including a set of primary windings connectedto the ac input, a first set of secondary windings connected to theregulator output, and a second set of secondary windings connected tothe controllable shunt reactance.

It is another object of the invention to provide a polyphase voltageregulator circuit of the above character wherein differences in theconfigurations of the windings are utilized to reduce the ripple contentof the regulated d-c output voltage.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a preferred embodiment of the circuitof the invention,

FIG. 2 is a schematic diagram of an alternative embodiment of a portionof the circuit of FIG. 1,

FIG. 3 is a schematic diagram of an alternative embodiment of anotherportion of the circuit of FIG. 1, and

FIGS. 4 through 7 illustrate various exemplary voltage and currentwaveforms produced by the circuit of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, there is shown a voltage regulating circuit 10 forsupplying a regulated d-c voltage to the terminals 11 and 12 of a d-cload 13 from the unregulated a-c voltage which a polyphase source 14establishes at a-c input terminals A, B and C. Regulating circuit 10includes a series regulating network which here takes the form of a lineinductance 15 for supporting the difference between the unregulated a-cinput voltages at terminals A, B and C and the regulated d-c outputvoltage at terminals 11 and 12. Line inductance 15 may comprise threeseparate substantially equal inductors connected between terminal pairsB-B1, A-A1 and C-C1 or, alternatively, may consist of three coupledwindings 15B, 15A and 15C which are located on a single magnetic core.

Regulating circuit 10 also includes a controllable shunt reactancenetwork 17 for inducing across line inductance 15 voltages equal to thedifference between the available unregulated a-c input voltages and theregulated output voltage. As will be described more fully presently,reactance network 17 serves as a shunt regulating network which controlsthe voltage across inductance 15 by drawing therethrough, from source14, a reactive current of controllable magnitude. Thus, seriesregulating network 15 and shunt regulating network 17 comprisecooperating portions of the power handling part of the circuit of theinvention.

Regulating circuit 10 also includes a suitable three-phase rectifyingnetwork 21 which converts the a-c voltage at terminals B2, A2 and C2 toa d-c voltage at output terminals 11 and 12. It will be understood thatif only an a-c output voltage is required, the desired output voltageand current may be drawn from terminals B2, A2 and C2. In the latterevent, the current rating of the diodes of network 21 may be greatlyreduced since they will conduct no load current. Alternatively, if bothan a-c and d-c output voltages are required, d-c output 11-12 and a-coutput B2, A2 and C2 may be used simultaneously.

Also forming an important part of regulating circuit 10 is a polyphasetransformer 19 which, in the present illustrative embodiment, includes aset of three Y-connected primary windings PA, PB and PC, a first set ofthree Y-connected secondary windings 1SA, 1SB and 1SC, and a second setof three delta-connected secondary windings 2SA, 2SB and 2SC.Preferably, transformer 19 should be constructed so that the threewindings identified with the letter A are located on one leg of thetransformer core and so that the three windings identified with theletters B and C are located on respective second and third legs of thecore.

Transformer 19 serves a variety of functions. Firstly, it allows theregulated output voltage to be higher or lower than the polyphase a-cinput voltage, depending upon the turns ratios between primary windingsPA, PB and PC and secondary windings 1SA, 1SB and 1SC. Secondly,transformer 19 allows the voltages at terminals A3, B3 and C3 of shuntregulating network 17 to be higher or lower than the a-c input voltages,depending upon the turns ratios between primary windings PA, PB and PCand secondary windings 2SA, 2SB and 2SC. Thirdly, transformer 19 servesa waveshaping function, i.e., causes the waveforms of the a-c voltagesat terminals B2, A2 and C2 to be different from the waveforms of thevoltages which network 17 applies to secondary windings 2SA, 2SB and2SC. This waveshaping is utilized to reduce the ripple content of thed-c output voltage upon rectification by network 21.

The schematic diagram of the circuitry shown in FIG. 1 is similar to theschematic diagram of the circuitry shown and described in my earlierpatent. For example, both the circuit of FIG. 1 and the circuit of myearlier patent include shunt reactance networks having a similarschematic representation. In addition, both the circuitry of FIG. 1 andthe circuitry shown in my earlier patent include series-connected lineinductances and three phase rectifying networks. The circuit elementswhich are utilized in constructing the regulator circuitry shown in FIG.1 and that shown in my earlier patent are, however, quite different.More particularly, the circuitry of the present invention is preferablyconstructed with magnetic units including only ordinary core materialsand ordinary winding configurations, with capacitors which need not havelow distributed inductances and with semiconductor devices which haveonly ordinary turn-on and turn-off characteristics. The circuitry of myearlier patent, however, utilizes magnetic units, capacitors andsemiconductor devices which have special characteristics and which aresubstantially more expensive than those utilized in the circuit ofFIG. 1. In addition, the circuitry of the present invention is governedby different time relationships and operates within a range offrequencies which excludes operation in the manner described in myearlier patent. Thus, the circuitry of the present invention and thatshown in my earlier patent are less similar than a visual comparison oftheir schematic diagrams would indicate.

In spite of the fact that the circuit of FIG. 1 costs substantially lessthan that of my earlier patent and utilizes time relationships whichcontravene the time relationships described therein, I have found thatit has regulating properties which are equal to and in some cases betterthan the regulating properties of the circuitry described in my earlierpatent. In addition, the circuitry of the present invention producessubstantially less audible noise and mechanical vibration than thecircuitry of my earlier patent. Finally, the circuitry of FIG. 1produces waveforms of lower harmonic content and, consequently, haslower harmonic power dissipation. Thus, the circuitry shown anddescribed herein is a significant improvement over the circuitry of myearlier patent.

As shown in FIG. 1, the terminals A3, B3 and C3 of shunt reactance 17are coupled to the load side of inductor 15, i.e., to terminals A1, B1and C1, through transformer 19. In addition, source 14 is coupled toterminals A1, B1 and C1 through inductor 15. Finally, terminals A1, B1and C1 are coupled to terminals A2, B2 and C2, through transformer 19.As a result of these connections, the voltages at terminals A2, B2 andC2 are equal to the algebraic sums of the voltages at input terminals A,B and C and the voltages appearing across inductor windings 15A, 15B and15C, respectively, multiplied by the turns ratios between primarywindings PA, PB and PC and secondary windings 1SA, 1SB and 1SC. Anadditional result is that the voltages across inductor windings 15A, 15Band 15C are dependent upon the magnitudes of the reactive currents whichcapacitors CA, CB and CC draw from source 14, through inductance 15.

In the present embodiment, capacitors CA, CB and CC are preferablychosen to present to input terminals A, B and C capacitive reactanceswhich are three times the inductive reactances presented to thoseterminals by the windings of inductance 15, causing the last-namedreactive currents to lead the a-c input voltages by 90°. Since the flowof such reactive currents through inductor 15 induces across windings15A, 15B and 15C voltages which add to respective phases of the a-cinput voltage, the a-c voltages at terminals A1, B1 and C1 will be seento be higher than the voltages at terminals A, B and C and to varydirectly in accordance with the magnitudes of those reactive currents.

Based upon the above-described connections and magnitude relationships,a variety of explanations may be advanced to account for the regulatingactivity of the circuit of FIG. 1. On the one hand, network 17 may bevisualized as an electronically adjustable three-phase capacitor, themagnitude of which is adjusted in accordance with the regulated outputvoltage. From this viewpoint, changes in the capacitance of thethree-phase capacitor change the magnitudes of the reactive currentswhich this capacitor draws from source 14, through inductor 15, andvoltage regulation may be visualized as the result of the variablecapacitors drawing, through inductor 15, reactive currents which havemagnitudes just sufficient to induce across that inductor the differencebetween the unregulated a-c input voltages at terminals A, B and C andthe regulated voltages at terminals A1, B1 and C1 (or A2, B2 and C2 or11 and 12).

On the other hand, network 17 may be visualized as a virtual three-phasevoltage generator the voltages of which lag the a-c input voltages by avariable phase angle. From this viewpoint, the voltages betweenterminals A3, B3 and C3 may be visualized as the output voltages of thevirtual generator and voltage regulation may be visualized as the resultof the action of the actual source 14 and the phase-shifted virtualsource 17 on inductor 15. In this view, virtual source 17 draws itsoperative energy from source 14 by way of the in-phase component of thecurrent which network 17 draws from source 14, and the voltages whichmust be induced across inductor 15 to support the difference between theunregulated voltages at terminals A, B and C and the regulated voltagesat terminals A1, B1 and C1 are induced by the flow of reactivecirculating currents between sources 14 and 17. This view isparticularly useful in understanding how variations in the powersupplied to the load result from changes in the angle by which thevoltages of virtual source 17 lag the voltages of actual source 14. Adetailed description of this power control mechanism may be found inU.S. Pat. No. 3,576,443 granted in my name on Apr. 27, 1971.

In practice, it makes no difference which of these views is adopted.Accordingly, for purposes of this description, terminology stemming fromeither or both views will be used, depending upon which terminology mostconveniently describes the subject matter then under discussion.

To the end that shunt reactance network 17 may draw from source 14,through inductor 15, reactive currents which cause the differencebetween the a-c input voltages and the regulated output voltage toapppear across the windings of line inductor 15, or, alternatively, tothe end that shunt reactance network 17 may vary the phase angle betweenthe voltages which it applies to inductor 15, through transformer 19,and the input voltages at input terminals, B, A and C, network 17includes a plurality of capacitors CA, CB and CC which are connected toone another in a delta-configuration. Network 17 also includes aplurality of thyristor switches SA1, SB1, SC1, SA2, SB2 and SC2 whichare connected to one another as a polyphase bridge network havingpolyphase input terminals BA, BB and BC and having d-c output terminalsD1 and D2 connected across a suitable discharge inductor DL.

In controlling the circuitry of FIG. 1 in accordance with the principlesof the present invention, thyristors SA1 through SC2 are fired, two at atime, in a predetermined, recurring sequence by firing signals from asuitable firing signal generating network 23. As will be described morefully presently, varying the phase angle between these firing signalsand the a-c input voltages at terminals A, B and C can vary themagnitudes of the reactive currents which capacitors CA, CB and CC drawfrom source 14, through inductor 15, and thereby vary the voltages atterminals A1, B1 and C1. For convenience, this angle will hereinafter bereferred to as the power or control angle. In addition to varying themagnitude of reactive current flow, varying the control angle can alsovary the power which source 14 can furnish to load 13, through inductor15. In accordance with the present invention, the control angle isvaried in accordance with the desired output voltage so that the outputvoltage has a constant value over a wide range of input voltages andoutput power levels.

In the present embodiment, the firing signals for thyristors SA1 throughSC2 are generated by a suitable firing signal generating network 23.Preferably, network 23 has inputs 25a, 25b and 25c which are connectedto input terminals A, B and C to allow the phase position of the inputvoltages to be determined and an input 27 which is connected to theregulator output to allow the sensing of output voltage variations. Aninput 29 may also be connected to the regulator output to sense theregulator output currents for current limiting purposes. While anyfeedback control network which fires thyristors SA1 through SC2 at thetimes necessary to maintain the output voltage at the desired value maybe utilized, the preferred form of firing signal generating means 23, isas shown in my co-pending U.S. patent application, Ser. No. 514,849,filed Oct. 15, 1974, now U.S. Pat. No. 3,922,594 entitled "ControlSystem For Phase Displacement Regulator Circuits", the disclosure ofwhich application is hereby expressly incorporated herein by reference.

As previously described, it is desirable that the circuit of FIG. 1produce d-c and/or a-c output voltages having a relatively low ripplecontent. In addition, it is desirable that the circuit of FIG. 1 notrequire the utilization of components having special operatingcharacteristics such as short turn-on and turn-off times. In accordancewith the present invention, these objectives are accomplishedsimultaneously.

One feature which allows this simultaneous result is the selection ofvalues for capacitors CA, CB and CC and inductor DL such that theperiodic firing of thyristors SA1 through SC2 results in the relativelyslow periodic redistribution of charge among capacitors CA, CB and CC ina series of discrete resonant discharge and recharge or chargeredistribution events. Each of these redistribution events ischaracterized by the flow of a pulse of current having a form whichapproximates that of the positive half of a sinusoid and having afrequency determined by any of capacitors CA, CB or CC and inductor DL.In order to facilitate reference to the preferred relationship which thea-c input frequency bears to the frequency fixed by any of capacitorsCA, CB or CC and inductor DL, the latter frequency will hereinafter bereferred to as the "resonant discharge frequency" or "discharge pulsefrequency".

Another cooperating feature which allows the above two objectives to beachieved simultaneously is the proper selection of windingconfigurations for transformer 19. Particularly when a d-c output isutilized, the selection of transformer winding configurations can resultin transformer 19 performing a waveshaping action which causes thevoltages at terminals A2, B2 and C2 to have waveforms which producenegligible ripple upon rectification by network 21, as will be seenlater in connection with FIGS. 6 and 7. This selection of transformerwinding configurations can also be of some importance if only a-c outputvoltages are desired, but, in that event, the waveshaping action oftransformer 19 is less important.

Within the above-described class of circuits, I have found that the mosteffective circuit configuration is one which utilizes the transformerconfiguration shown in FIG. 1, i.e., Y-connected primary and firstsecondary windings and delta-connected second secondary windings. Itwill be understood, however, that advantageous but less desirabletransformer configurations may be utilized, for example, the transformerconfiguration shown in FIG. 2.

CIRCUIT WAVESHAPES

Referring to FIG. 4, there are shown the waveforms of the voltagesacross capacitors CA, CB and CC and, therefore, across secondarywindings 2SA, 2SB and 2SC when the resonant discharge frequency isslightly greater than three times the frequency of the voltages atinputs B, A and C and when the latter voltages are relatively high. Aswill be described more fully later, the waveforms of the voltages shownin FIG. 4 are affected by the magnitude of the input voltage and theoutput power, but these effects are ordinarily not extreme for the inputvoltage and output power ranges normally encountered in regulatorcircuit design.

Referring to V_(2SC), the voltage across secondary winding 2SC, it willbe seen that between times T_(A) -T_(B), voltage V_(2SC) reverses from+E/2 to -E/2, that voltage V_(2SB) across secondary winding 2SBdecreases from -E to -E/2 and that voltage V_(2SA) across secondarywinding 2SA increases from +E/2 to +E. All three of these changes involtage comprise a charge redistribution event EV1 and result from theturn-on of thyristors SA1 and SC2 at time T_(A) and the turn-off ofthese same thyristors just prior to time T_(B). The reversal of voltageV_(2SC) results from the resonant discharging and recharging ofcapacitor CC through the path including thyristor SA1, inductor DL andthyristor SC2. The changes in voltages V_(2SA) and V_(2SB) occur as avoltage reaction to reversal in the voltage across capacitor CC, sincethe sum of the voltages across capacitors CA, CB and CC must be equal tozero.

Similarly, between times T_(B) and T_(C), the voltage V_(2SB) acrosssecondary winding 2SB reverses from -E/2 to +E/2. During the same periodof time, V_(2SA) and V_(2SC), the voltages across secondary windings 2SAand 2SC change by E/2. All three of these changes in voltage comprise aredistribution event EV2 and result from the turn-on of thyristors SB1and SC2 at time T_(B) and the turn off of these same thyristors justprior to time T_(C). The reversal of voltage V_(2SB) results from theresonant discharging and recharging of capacitor CB through the pathincluding thyristor SB1, inductor DL, and thyristor SC2. The changes involtages V_(2SA) and V_(2SC) occur as a voltage reaction to the reversalin the voltage across capacitor CB, since the sum of the voltages acrosscapacitors CA, CB and CC must be equal to zero.

It will be understood that during time intervals T_(C) -T_(D), T_(D)-T_(E), T_(E) -T_(F) and T_(F) -T_(G), additional charge redistributionevents EV3, EV4, EV5 and EV6 occur and that following chargeredistribution event EV6, the voltages shown in FIG. 4 will once againbe at the values which they had at time T_(A). The sequence of thyristorfirings which give rise to the voltage waveforms shown in FIG. 4 areshown in FIG. 4 together with arrows indicating the times at which thosethyristors are fired. Thus, six charge redistribution events areinitiated by the firing of six pairs of thyristors to establish onecomplete cycle of the voltages shown in FIG. 4.

In the preferred embodiment of the invention shown in FIGS. 1 and 4, thedischarge pulse frequency is slightly greater than three times thefrequency of the a-c input voltage. As a result, under the conditionswhich exist when the waveforms shown in FIG. 4 are produced, each chargeredistribution event such as EV1 begins and ends in slightly less than60° of the input voltage. During the time between the end of oneredistribution event and the beginning of the next redistribution event,e.g., between the time when thyristors SA1 and SC2 turn off at the endof EV1 and the time that thyristors SB1 and SC2 turn on at the beginningof EV2, the current in inductor DL is equal to zero since thyristors SA1through SC2 are all non-conducting. These zero current intervals areillustrated in FIG. 5(a) wherein I_(DL), the current through inductorDL, is plotted as a function of time.

Referring to FIGS. 5(b) and 5(c), there are shown V_(CA), the voltageacross capacitor CA, and I_(CA), the current through capacitor CA, andtheir relationship to the current through inductor DL. In comparingwaveforms V_(CA) and I_(CA), it is apparent that each change in thevoltage across capacitor CA is accompanied by a pulse of currenttherethrough. The larger ones of these pulses are labeled RDP toindicate that those pulses flow when capacitor CA resonantly dischargesthrough inductor DL. The smaller ones of these pulses are labeled VRP toindicate that those pulses flow as a result of a voltage reaction incapacitor CA to the resonant discharge of one of the other capacitorsthrough inductor DL. The current pulses through inductor DL, however,are all equal and all flow as a result of the resonant discharge of oneor another of capacitors CA, CB or CC. Thus, when the resonant dischargefrequency is slightly greater than three times the frequency of the a-cinput voltage, the current through inductor DL and the current througheach capacitor comprises a series of discrete pulses of current, one setof capacitor current pulses being present for each charge redistributionevent.

In practicing the invention, the resonant discharge frequency may be ashigh as ten times the frequency of the a-c input voltage, withoutincurring certain of the disadvantages of the circuit of my earlierpatent. These higher discharge frequencies, however, reduce the numberof degrees of the input voltage which are occupied by each resonantdischarge pulse. As a result, both the zero current intervals ininductor current I_(DL) and the zero sloped portions of the capacitorvoltage waveforms will become wider. These changes in waveform increasethe harmonic content of the waveforms across the windings of transformer19 without any compensating improvement in the operative characteristicsof the circuit of FIG. 1 and are, consequently, less desirable than theutilization of resonant discharge frequencies which are within thepreferred frequency range of from three to six times the a-c inputvoltage frequency.

On the other hand, the resonant discharge frequency may be lower thanthree times the frequency of the a-c input voltage. As these lower pulsefrequencies are selected, however, each resonant discharge pulse willoccupy more than 60° of the input voltage. As a result, the currentthrough discharge inductor DL will become continuous, i.e., will notfall to zero, and the zero-sloped portions of the capacitor voltageswill disappear entirely. While operation within this range of dischargefrequencies does not prevent the utilization of the circuit of FIG. 1 asa voltage regulator, it causes the circuitry to exhibit a dynamicresponse which is significantly slower than that provided when thedischarge frequency is within the preferred frequency range of fromthree to six times the frequency of the a-c input voltage.

In view of the foregoing, it will be seen that while the circuit of FIG.1 may be operated with resonant discharge frequencies which are lessthan three times or more than ten times the a-c input voltage frequency,the circuitry of the invention contemplates operation at resonantdischarge frequencies within those limits and, in the preferred form ofthe invention, contemplates operation at resonant discharge frequencieswhich are three to six times the a-c input voltage frequency.

As previously described, it is desirable that the rectification of theregulated a-c voltage at terminals B2, A2 and C2 provide a d-c outputvoltage which has a relatively low ripple content. This low ripplecontent is desirable not only because it allows the regulator circuitryof the invention to be constructed without incurring the expense ofheavy output filtering, but also because the absence of heavy outputfiltering allows the voltage regulating circuitry to have a dynamicresponse which is quite rapid, e.g., on the order of 20 milliseconds. Inaccordance with the present invention, the need for heavy output voltagefiltering is eliminated as a result of the combined effect of theabove-described frequency relationship and the connection of firstsecondary windings 1SA, 1SB and 1SC in a Y-configuration.

Referring to FIG. 6a, there is shown voltage V_(A2-B2) , the voltagefrom a-c output terminal A2 to a-c output terminal B2. Because of theY-configuration of windings 1SA, 1SB and 1SC, this voltage is equal tothe sum of the voltage from terminal A2 to terminal N2 and the voltagefrom terminal N2 to terminal B2. Stated differently, voltage V_(A2-B2)is equal to the voltage from terminal A2 to terminal N2 minus thevoltage from terminal B2 to terminal N2. The fact that the twolast-named voltages combine to establish the flat-topped waveform shownin FIG. 6a may be verified by adding the voltages shown in FIGS. 6b and6c. It will be understood that the waveforms of voltages V_(B2-C2) andV_(C2-A2) are of similar waveshape, but lag voltage V_(A2-B2) by 120°and 240°, respectively, as shown in FIG. 7. Thus, the coupling ofdelta-connected secondary windings 2SA, 2SB and Y-connected secondarywindings 1SA, 1SB and 1SC causes the waveforms of voltages at a-cterminals A2, B2 and C2 to be different from the waveforms of thevoltages at a-c terminals A3, B3 and C3.

Referring to FIG. 7, it will be seen that, ideally speaking, at leastone of the three flat-topped voltages at terminals B2, A2 and C2 is atits peak value at all times. Because of this fact, and becauserectifying network 21 is a full-wave rectifier network, the regulateda-c voltages at terminals A2, B2 and C2 produce a regulated d-c voltageupon rectification by network 21. Thus, the d-c output voltage atterminals 11 and 12 has a value substantially equal to the peak value ofthe regulated a-c voltages at terminals B2, A2 and C2 and issubstantially free of ripple.

In practice, the d-c voltage appearing at the output of rectifyingnetwork 21 may require filtering before it is applied to a load havingstringent ripple limitations. One reason why this filtering may benecessary is that source 14, acting through line inductor 15, can causea component of current having a frequency equal to the a-c inputfrequency to flow through capacitors CA, CB and CC during each chargeredistribution event. This component of current, in turn, causes thewaveforms of the voltages across transformer 19 to be distorted somewhatfrom the shapes shown in FIG. 4. With proper selection of values forcomponents 15 and capacitors CA, CB and CC, however, the effect of thisdistortion can be eliminated with only light output voltage filtering.

OUTPUT VOLTAGE REGULATION

The start-up and voltage regulating activity of the circuit of FIG. 1will now be described. As voltage is initially applied to a-c inputterminals A, B and C, a-c transient voltages and currents begin toappear across and through the windings of inductor 15 and, throughtransformer 19, across and through capacitors CA, CB and CC. Assumingthat thyristors SA1 through SC2 are initially non-conducting, thevoltages at terminals A1, B1 and C1 will rise toward the steady-statea-c values which they would attain if the last-named thyristors remainednonconducting. Ordinarily, these steady-state voltages will be higherthan those necessary to furnish the desired output voltage. This rise tothose higher voltages is stopped at the proper output voltage value bythe switching activity of thyristors SA1 through SC2, which thyristorscooperate with inductor DL to effectively cancel that portion of thecapacitance of capacitors CA, CB and CC which would allow the outputvoltage to rise to too high a value.

More particularly, as the output voltage rises, thyristors SA1 throughSC2 and inductor DL begin to increase the capacitive reactance whichcapacitors CA, CB and CC present to source 14 and thereby begin tooppose increases in the magnitudes of the reactive currents that network17 draws from source 14, through inductor 15. As a result, the inducedvoltages across inductor 15 and the voltages at terminals A1, B1 and C1begin to approach their final, desired values more slowly. it will beunderstood that as the voltages at terminals A1, B1 and C1 attain thedesired values, a condition is attained in which the switching activityof thyristors SA1 through SC2 is just sufficient to induce acrossinductor 15 the difference between the unregulated input voltages andthe desired output voltage. After the latter condition is attained, itis maintained, over a wide range of input voltages and output powerlevels, by the voltage regulating activity of the circuit of theinvention, as will now be explained.

Assume, as an example, that the input voltage is at its nominal valueand that source 14 is supplying no load power through inductance 15.Under these conditions, firing signals are applied to network 17 atabout the same times that the a-c input voltages cross through zero. Asa result, the capacitor voltages will cross through zero approximately30°later, i.e., later by one-half of a 60° resonant discharge event, asshown in FIGS. 5a and 5b. Because, as shown for a representative pair ofvoltages in FIGS. 6a and 6b, the voltages at terminals A1, B1 and C1,lead the capacitor voltages by 30°, the zero-crossings of the voltagesat terminals A1, B1 and C1 will occur at approximately the same times asthe zero-crossings of the voltages at terminals A, B and C.Consequently, the power angle will be approximately equal to zero and noload power will be delivered. In practice, some small power angle willappear to allow source 14 to furnish the operating losses of the circuitof FIG. 1.

At the same time, since the input voltages are at their nominal valuesand are approximately in phase with the voltages at terminals A1, B1 andC1, the difference between the latter voltages will appear across thewindings of inductance 15 and have values which are between low voltageswhich appear thereacross under high input voltage conditions and thehigher voltages which appear thereacross under low input voltageconditions. This condition exists because the switching activity ofthyristors SA1 through SC1 is such that the magnitudes of the reactivecurrents drawn by network 17 are between the low magnitude currentswhich flow therethrough under high input voltage conditions and the highmagnitude currents which flow therethrough under low input voltageconditions. At the same time, the average value of the current ininductor DL will be between the high values of average current whichflow therethrough under high input voltage conditions and the low valuesof average current which flow therethrough under low input voltageconditions.

If, under the above conditions, the input voltages should decrease, thevoltages at terminals A1, B1 and C1 will also decrease. The latterdecrease in voltage will, in turn, cause control network 23 to retardthe phase position of the firing signals in relation to the inputvoltages and thereby cause the power angle to increase. As a result,source 14 will begin to supply real power through inductance 15. Sincecapacitors CA, CB and CC are the only circuit elements capable ofreceiving this energy, they will do so and thereby force the voltages atterminals A1, B1 and C1 to return to their original higher values. Theability of network 23 to advance the phase position of the firingsignals, and thereby remove this energy from the capacitors, serves toprevent the voltages at terminals A1, B1 and C1 from rising beyond theiroriginal values. Thus, as the input voltages decrease from their nominalvalues, the phase position of the firing signals is changed by an amountjust sufficient to keep the output voltage at the desired value.

During the above-described change in phase position, there also occurincreases in the reactive currents which network 17 draws from source14, through inductance 15. These increased reactive currents in turnincrease the induced voltages across inductance 15 to reflect theincreased difference between the new, lower input voltage and theregulated output voltage. At the same time, the average current throughinductor DL decreases, in accordance with the increase in reactivecurrent flow, to reflect an increase in the effective capacitance whichcapacitors CA, CB and CC present to source 14. Thus, as the inputvoltages decrease from their nominal values, the reactive currentsthrough inductance 15 rise and the average current through inductor DLfalls.

It will be understood that if the input voltages should rise to abovetheir nominal values, the phase position of the firing signals will beadvanced in phase in relation to the input voltages by an amount justsufficient to establish the regulated output voltage at the new highervalues of input voltage. Under these conditions, however, the reactivecurrents drawn by network 17 will have relatively low values and theaverage current through inductor DL will have a relatively high value.

The operation of the regulator circuit of the invention in the presenceof load current flow is similar to that just described in connectionwith input voltage changes. In the presence of load current flow,however, the change in power angle is greater, since it includes acomponent which reflects the load power being supplied as well as acomponent which results from the previously described angular adjustmentfor input voltage changes. Accordingly, the operation of the circuit ofFIG. 1 in the presence of changes in load current will not be describedin detail herein.

In operating with the circuit of FIG. 1, control network 23 generatespairs of firing signals which, under steady-state conditions, areseparated from the preceding and following pair of firing signals by 60°of the a-c input voltage. The phase angle between the firing signals asa whole and the a-c input voltages, however, is dependent upon themagnitude of the input voltage and the output current. As the magnitudeof the input voltages or the output current change from the abovevalues, the firing signals will assume new phase relationships to theinput voltage and thereby restore the output voltage to the desired,regulated value. During this period of phase adjustment, successive setsof firing signals may be separated by more or less than 60° of the inputvoltage, but this will be true only until the new steady-state phaseposition is attained. Thereafter, successive sets of firing signals willonce again be separated by 60° of the input voltage, but the set offiring signals as a whole will be located in a different phase positionwith respect to the input voltages. These control characteristicstogether with other desirable characteristics such as limits on the rateof change of phase angle are advantageously provided by the controlcircuitry described in my previously mentioned copending application.

While the circuitry of FIG. 1 illustrates the preferred form ofcontrollable shunt reactance 17, any suitablecapacitive-inductive-switching network having similar operativecharacteristics may be utilized in place thereof. FIG. 3 illustrates onesuch alternative controllable shunt reactance network 17'. In the latternetwork, the function of inductor DL of FIG. 1 may be served by thesubstantially equal separate inductors DL1, DL2 and DL3 or may be servedby a single, polyphase inductor having three coupled windings arrangedin the manner shown in FIG. 3. In addition, the function of thyristorsSA1 through SC2 is served by triacs SA through SC. It will be understoodthat the firing pattern for triacs SA through SC is similar to butsimpler than that utilized for thyristors SA1 through SC2 and may beeasily derived therefrom.

In view of the foregoing, it will be seen that the circuit of theinvention comprises an improved voltage regulator circuit which utilizesnovel time and transformer winding relationships to afford improvedelectrical performance and efficiency while at the same timesubstantially reducing circuit costs.

It will be understood that the foregoing embodiments of the inventionhave been shown for illustrative and descriptive purposes only and thatthe full scope of the present invention is as set forth in the appendedclaims.

What is claimed is:
 1. A voltage regulator circuit comprising incombination, an a-c input for connection to a source of a-c voltage, anoutput for connection to a load, first inductance means for supporting avoltage dependent upon the difference between the a-c voltage at theinput and the voltage at the output, a transformer having a set ofprimary windings, a first set of secondary windings and a second set ofsecondary windings, means for connecting the first inductance meansbetween the a-c input and the primary windings, means for connecting thefirst set of secondary windings to the output, at least three capacitorsconnected in a closed circuit path, the sum of the capacitor voltagesaround said closed circuit path being equal to zero, means forconnecting the second set of secondary windings to the capacitors,second inductance means for conducting the flow of a resonant dischargecurrent through each capacitor, the resonant discharge frequency of theresonant discharge current being determined by the second inductancemeans and the capacitors and being greater than three but no more thenten times greater than the frequency of the voltage at the input,controllable switching means for initiating and terminating the flow ofa resonant discharge current through each capacitor and thereby forcinga redistribution of charge among the then remaining capacitors, controlmeans for generating firing signals for the controllable switching meansand for varying the phase position of said firing signals in accordancewith the voltage at the output to maintain the voltage at the output ata substantially constant value.
 2. A voltage regulator circuit as setforth in claim 1 wherein the means for connecting the first set ofsecondary windings to the output includes rectifying means forestablishing at the output a d-c voltage the magnitude of which variesin accordance with the magnitude of the a-c voltage on the first set ofsecondary windings.
 3. A voltage regulator circuit as set forth in claim1 wherein the resonant discharge frequency is greater than three and nomore than six times greater than the frequency of the voltage at theinput.
 4. A voltage regulator circuit as set forth in claim 3 whereinthe set of primary windings comprises three Y-connected windings,wherein the first set of secondary windings comprises three Y-connectedwindings and wherein the second set of secondary windings comprisesthree delta-connected windings.
 5. A voltage regulator circuit as setforth in claim 3 wherein the controllable switching means comprises athyristor bridge having a-c input terminals connected to the capacitorsand having d-c output terminals connected to the second inductancemeans.
 6. A voltage regulator circuit as set forth in claim 1 whereinthe set of primary windings comprises three Y-connected windings,wherein the first set of secondary windings comprises three Y-connectedwindings and wherein the second set of secondary windings comprisesthree delta-connected windings.
 7. A voltage regulator circuit as setforth in claim 1 wherein said controllable switching means is connectedbetween the capacitors and the second inductance means so as toestablish a unidirectional current flow through the second inductancemeans.
 8. A voltage regulator circuit comprising, in combination, athree phase a-c input for connection to a three-phase source of voltage,an output for connection to a load, line inductance means for supportinga voltage dependent upon the difference between the three-phase voltageat the a-c input and the voltage at the output, said line inductancemeans including at least three windings, a transformer having a set ofthree primary windings, a first set of three secondary windings and asecond set of three secondary windings, means for connecting respectivewindings of the line inductance means between respective phases of thea-c input and the primary windings, means for connecting the first setof three secondary windings to the output, at least three capacitorsconnected in a closed circuit path, the sum of the capacitor voltagesaround said closed circuit path being equal to zero, means forconnecting the second set of three secondary windings to the capacitors,discharge inductance means for conducting the flow of a resonantdischarge current pulse through each capacitor, the resonant dischargefrequency of the current pulses being determined by the dischargeinductance means and the capacitors and being no less than three and nomore than ten times greater than the frequency of any phase of thevoltage at the a-c input, controllable switching means for sequentiallyinitiating and terminating the flow of a resonant discharge currentpulse through each capacitor and thereby redistributing charge among thethen remaining capacitors, control means for generating firing signalsfor the controllable switching means, the control means serving to varythe phase position of the firing signals in relation to the phaseposition of the voltages at the a-c input so as to maintain asubstantially constant voltage at the output.
 9. A voltage regulatorcircuit as set forth in claim 8 wherein the line inductance meansincludes a magnetic core upon which are disposed three windings havingsubstantially the same number of turns.
 10. A voltage regulator circuitas set forth in claim 8 including rectifying means for establishing ad-c voltage at the output, said d-c voltage having a magnitude whichvaries in accordance with the peak voltage across the first set ofsecondary windings.
 11. A voltage regulator circuit as set forth inclaim 8 wherein said resonant discharge frequency is greater than threeand less than six times the frequency of any phase of the voltage at thea-c input.
 12. A voltage regulator circuit as set forth in claim 11wherein the three primary windings are connected to one another in aY-configuration, wherein the first set of three secondary windings areconnected to one another in a Y-configuration and wherein the second setof three secondary windings are connected to one another in adelta-configuration.
 13. A voltage regulator circuit as set forth inclaim 8 wherein the controllable switching means comprises a thyristorbridge having a-c input terminals connected to the capacitors and havingd-c output terminals connected to the discharge inductance means.
 14. Avoltage regulator circuit as set forth in claim 8 wherein at least sixfiring pulses are applied to the controllable switching means duringeach full cycle of the voltages at the a-c input.
 15. A voltageregulator circuit comprising, in combination, a circuit input forconnection to a polyphase a-c source, a circuit output for connection toa load, polyphase line inductance means for supporting a voltagedependent upon the difference in voltages between the a-c voltages atthe circuit input and the voltage at the circuit output, a transformerhaving a set of polyphase primary windings, having a first set ofpolyphase secondary windings and having a second set of polyphasesecondary windings, means for connecting the line inductance meansbetween the circuit input and the primary windings, means for connectingthe first set of secondary windings to the circuit output, at leastthree capacitors connected in a closed circuit path such that eachcapacitor can exchange charge with each adjacent capacitor, thecapacitors serving as means for drawing a leading component of currentfrom the circuit input through the line inductance means and thetransformer, means for connecting the capacitors to the second set ofsecondary windings, controllable switching means for sequentiallyconducting a resonant discharge current pulse through each capacitor toreverse the polarity of the charge across that capacitor andredistribute charge among the then remaining capacitors, each resonantdischarge current pulse having a resonant discharge frequency of fromthree to ten times the frequency of the voltage at the circuit input,and control means for changing the phase relationship between saidresonant discharge current pulses and the voltages at the circuit input,in accordance with the voltage at the circuit output, to maintain thevoltage at the circuit output at a substantially constant value.
 16. Avoltage regulator circuit as set forth in claim 15 wherein the primarywindings comprise three Y-connected windings, wherein the first set ofsecondary windings comprise three Y-connected windings, wherein thesecond set of secondary windings comprise three delta-connected windingsand wherein the plurality of capacitors comprise three delta-connectedcapacitors.
 17. A voltage regulator circuit as set forth in claim 16wherein each resonant discharge current pulse has a resonant dischargefrequency of from three to six times the frequency of the voltage at thecircuit input.
 18. A voltage regulator circuit as set forth in claim 17including rectifying means for establishing at the circuit output a d-cvoltage having a magnitude approximately equal to the peak value of thevoltage across the first set of secondary windings.